A 2-pm CMOS Digital Adaptive Equalizer Chip for QAM Digital Radio Modems

With dlgitsdadaptiveequalizersthe performanceof a dlgkal radio modem for quadrature amplitude modulation (QAM,) can be improved considerably. In this paper the design and fabrication of a fully digitaf adaptive equalizer chip for QAM digitaf radio modems is reported. The chip contains 107936 transistors on a silicon area of 94.6 mmz. The chip was designed in a 2-pm CMOS technology for a clock and sampling rate of 23.5 MHz. Accordingly the functiorraf throughput rate per chip area is 6.7 101’ equivalent gates Hz/cm*. The inputs and outputs of the chip are ECL compatible, using a control unit compensating the influence of transistor parameter variations. For proper communication between chips having different technology parameters, a matched clocking scheme for synchronization was developed. As a high degree of verification certainty was reached in tke verification of the design, first silicon was working and first samples have been tested iu an experimental 16-QAM digital radio modem running at 35-MH2 clock and sampling rate.